Experimenting with logicly
Logicly, the demo for which can be found here, is a very useful logic gate simulator which can allow you to create complex logic systems without the need for electrical engineering level knowledge of using hundreds of transistors and resistors correctly. My first task with this simulator is to emulate a stepping motor, by using the gates to control which solenoids have a voltage when. This was a fairly simple affair, involving only one flip flop and nine gates. The "circuit" is pictured below.The first thing one might notice is that there are in fact no solenoids in this model - within the constraints of the program, data can be outputted as a lightbulb or a binary-configured digit, so I chose the former of the two. Another thing is that, since a lightbulb has only two states ("on" and "off"), there cannot be room for the three solenoid states of "positive", "neutral" and "negative": however, assuming that we are looking at the negative end of the rotor, the negative solenoid state is merely used to achieve a higher torque, so it can be dismissed here - therefore in this model, "on" represents "positive", and "off" represents "neutral". The full working of the circuit is below, through its 4 states.
Clearly the solenoid configuration changes every second, controlled by the four AND gates. However whether this translates into a tick every second depends on the number of teeth on the rotor and stator - in the previous post I found that a 30-28 motor that turns by rotating the field 45° will move 30 rotor teeth in 120 rotations, so the clock could instead take an input of 1Hz in order to turn 360° in 60 seconds. This would involve using only 15 flip flops in the frequency division of the 32768Hz quartz oscillator, as opposed to the implicit 16 here.
The next section is optional, as you may well understand exactly how I have reached this result with the gates. If so, click here to jump to the next part of the post.
FULL EXPLANATION OF THE CIRCUIT [OPTIONAL]
The "clock" here gives an output of 0.5Hz, meaning that a logic 1 is pulsed for a 1 second duration, starting every 2 seconds. This will be fed into a buffer, passing on the value of the clock at any given time, and a NOT gate which will pass on the inverse of this. In addition the "clock" will act as the clock for the T flip flop - since the PRE' and CLR' functions are negative-edge triggered, I have disabled the former by attaching it to a logic 1 input, and made the clear function operable by connecting the output of a push button to a NOT gate (i.e. the negative edge will occur when the button is pressed, acting as a reset function); the flip flop is in toggle mode, since the T input is connected to logic 1. The Q output of the flip flop, just like the "clock", is fed into a buffer and a NOT gate to form "T" and "NOT-T".Next I produced a truth table for the circuit so far, plotting the discrete time intervals of the "clock" against the values of "Clock", "NOT-Clock", "T" and "NOT-T":
This doesn't seem to throw any light upon the situation, but placing 4 AND gates in certain combinations does:
From here we have a situation where one, and only one, AND gate produces a logic 1 output in each second. These can be hooked up to sequential opposite pairs of lightbulbs to produce the desired pattern shown in the video.
"Stepping" it up a notch
Without alternative output options on the simulator, I have reached the end of what I can do with analog clocks. However, since a digit is the other output option, there is a wealth of potential within the realm of the digital clock. A huge amount of experimentation and tweaking, plus some attempts to make the whole circuit neater and more logically structured, has led to the creation of my basic 24-hour clock system, shown below.FULL EXPLANATION OF THE CIRCUIT [OPTIONAL]
This circuit is clearly more complex, and will take a huge amount of explaining: we will start with the far right hand of the circuit and work our way back. I have tried to make the diagram more clear by isolating the circuitry for each digit into blocks, but to be honest it still made a fairly unavoidable tangle...
Digit 1
The input comes from the 0.5Hz clock, the NOT value of which forms the first binary input of the digit. This clock is also used to trigger the (2^-2)Hz flip flop, the inverse output of which forms the second binary clock input. The Q output of the flip flop feeds into the next flip flop, and the process repeats for (2^-3)Hz and (2^-4)Hz. The most annoying thing about these digits is the same thing that makes them so convenient - they are binary. Since the number of possible numerical outputs follows the function n = 2x (where x = number of digit inputs), there must be 4 pins to allow all the numbers from 0-9 to be displayed (2 cubed is only 8). Unfortunately this also generates a surplus of 6 characters (A-F), so using the flip flops as they are causes the digit to count from 0 to F before resetting to 0. We only want 0-9, so some jiggery-pokery is required. I have therefore created a test, comprised of an OR gate, an AND gate and a NOT gate, which will tell when the character A is reached and will instead reset all the flip flops to 0. The OR gate returns a logic 1 if output 2 or 3 is logic 1, and the AND gate will return a logic 1 if the OR is 1 and output 4 is 1. In this case, the NOT gate will return a 0. The additional AND gate below it will allow the reset to occur either in this eventuality, or if the master reset button is pressed. The result of their of these cases is that the negative-edge triggered PRE' functions on each flip flop will be fed with a short pulse of logic 0, resetting every flip flop back to 0. The test on outputs 2, 3 and 4 works because every number higher than 9 (i.e. A-F) will have output 4 on, and either outputs 2 or 3 on too.
Digit 2
Digit 2 is fed the Q output from (2^-4)Hz to form the clock input for (2^-5)Hz. The same chain of events, which acts as an extended frequency divider circuit, will occur for digit 2. However there are 60 seconds in a minute, so we only want digit 2 to count from 0 to 5 - this involves a different version of the reset test explained earlier, comprised of 2 AND gates, an XOR gate and a NOT gate. The first AND gate will return 1 only if outputs 6 and 7 are both 1. The XOR gate will only return 1 if only one of outputs 5 and 6 are 1. The second AND gate will only return 1 if both the first AND gate and the XOR gate are 1. In this case, which has tested when the binary 0110 is reached (decimal 6), the NOT gate will return a value of 0, negative-edge triggering the PRE' functions for the four flip flops associated with digit 2, resetting them to 0 as before.
Digit 3
This digit has exactly the same wiring as digit 1, but has four flip flops because we do not have the benefit of the 0.5Hz clock input providing a 'free' output. The clock input to (2^-9)Hz is the Q output of (2^-8)Hz.
Digit 4
Since there are 60 minutes in an hour, this digit has the same wiring as digit 2, but takes the Q output from (2^-12)Hz as the clock input of (2^-13)Hz.
Digit 5
Things get even more funky here, because this digit will be required to tick from 0-9 twice (in 00-09 hours and 10-19 hours), then only 0-3 the third time (in 20-23 hours), before resetting to repeat the pattern. For this I have started by employing the reset-after-9 test, then I will return to this digit once I have built digit 6. Remember that the clock input for (2^-17)Hz is the Q output of (2^-16)Hz!
Digit 6
This digit is much more simple, because it only needs to tick 0-2 before resetting to zero. Therefore only two flip flops are required, and outputs 23 and 24 can be fixed at logic 0. As usual, the clock input for (2^-21)Hz is the Q output of (2^-20)Hz. The 0000 reset test for digit 6 involves testing for the binary 11 over outputs 21 and 22, which can be done with a single AND gate. In this case, the NOT gate will return a logic 0 which will negative-edge trigger the PRE' functions of the two flip flops associated with digit 6. A final test needs to be constructed as well though, to deal with the digit 5 irregularity - I have made a test for the situation where output 21 is logic 0 and output 22 is logic 1, using 2 XOR gates and an AND gate, which is fairly self explanatory when you look at the diagram. The creation of a logic 1 when both conditions are met feeds back into another AND gate at digit 5 - this will return 1 only if the digit 6 test is logic 1, and an OR gate comparing outputs 23 and 24 returns logic 1. In this case, the NOT gate will return 0, and this result feeds into a 3-input AND gate later on. This 3-input AND gate allows the PRE' functions to be triggered when the above conditions are met, when the master reset is pressed or if digit 5 reaches A in a [(digit 6) ≠ 2] situation.
I hope this makes my circuit easier to understand, but I imagine my explanation leaves something to be desired!